Re: [REVIEW] Re: Compression of full-page-writes

From: Ants Aasma <ants(at)cybertec(dot)at>
To: Florian Weimer <fw(at)deneb(dot)enyo(dot)de>
Cc: Arthur Silva <arthurprs(at)gmail(dot)com>, Fujii Masao <masao(dot)fujii(at)gmail(dot)com>, Robert Haas <robertmhaas(at)gmail(dot)com>, PostgreSQL-development <pgsql-hackers(at)postgresql(dot)org>, Andres Freund <andres(at)2ndquadrant(dot)com>, Rahila Syed <rahilasyed(dot)90(at)gmail(dot)com>, Rahila Syed <rahilasyed90(at)gmail(dot)com>, Abhijit Menon-Sen <ams(at)2ndquadrant(dot)com>, Heikki Linnakangas <hlinnakangas(at)vmware(dot)com>
Subject: Re: [REVIEW] Re: Compression of full-page-writes
Date: 2014-09-24 14:56:45
Message-ID: CA+CSw_t01hK-L2SSJT+Om7e70t2kXhayzJzCVK85xugri_V5yg@mail.gmail.com
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On Tue, Sep 23, 2014 at 8:15 PM, Florian Weimer <fw(at)deneb(dot)enyo(dot)de> wrote:
> * Ants Aasma:
>
>> CRC has exactly one hardware implementation in general purpose CPU's
>
> I'm pretty sure that's not true. Many general purpose CPUs have CRC
> circuity, and there must be some which also expose them as
> instructions.

I must eat my words here, indeed AMD processors starting from
Bulldozer do implement the CRC32 instruction. However, according to
Agner Fog, AMD's implementation has a 6 cycle latency and more
importantly a throughput of 1/6 per cycle. While Intel's
implementation on all CPUs except the new Atom has 3 cycle latency and
1 instruction/cycle throughput. This means that there still is a
significant handicap for AMD platforms, not to mention Power or Sparc
with no hardware support. Some ARM's implement CRC32, but I haven't
researched what their performance is.

Regards,
Ants Aasma
--
Cybertec Schönig & Schönig GmbH
Gröhrmühlgasse 26
A-2700 Wiener Neustadt
Web: http://www.postgresql-support.de

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