| From: | Robert Haas <robertmhaas(at)gmail(dot)com> |
|---|---|
| To: | Andres Freund <andres(at)2ndquadrant(dot)com> |
| Cc: | Bruce Momjian <bruce(at)momjian(dot)us>, Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us>, Greg Stark <stark(at)mit(dot)edu>, Peter Geoghegan <pg(at)heroku(dot)com>, PostgreSQL-development <pgsql-hackers(at)postgresql(dot)org> |
| Subject: | Re: Misaligned BufferDescriptors causing major performance problems on AMD |
| Date: | 2015-01-05 16:55:57 |
| Message-ID: | CA+TgmoaejssmRfkEQaVtsFMMAsmgbCV8UDinMRVCi_svbxgAYw@mail.gmail.com |
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| Lists: | pgsql-hackers |
On Thu, Jan 1, 2015 at 3:04 PM, Andres Freund <andres(at)2ndquadrant(dot)com> wrote:
>>That's true, but if you don't align the beginnings of the allocations,
>>then it's a lot more complicated for the code to properly align stuff
>>within the allocation. It's got to insert a variable amount of
>>padding based on the alignment it happens to get.
>
> Hm? Allocate +PG_CACHELINE_SIZE and do var = CACHELINEALIGN(var).
Meh. I guess that will work, but I see little advantage in it.
Cache-line aligning the allocations is simple and, not of no value, of
long precedent.
--
Robert Haas
EnterpriseDB: http://www.enterprisedb.com
The Enterprise PostgreSQL Company
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