Re: Latches with weak memory ordering (Re: max_wal_senders must die)

From: Aidan Van Dyk <aidan(at)highrise(dot)ca>
To: Andres Freund <andres(at)anarazel(dot)de>
Cc: Robert Haas <robertmhaas(at)gmail(dot)com>, pgsql-hackers(at)postgresql(dot)org, Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us>, Heikki Linnakangas <heikki(dot)linnakangas(at)enterprisedb(dot)com>, Bruce Momjian <bruce(at)momjian(dot)us>, Josh Berkus <josh(at)agliodbs(dot)com>
Subject: Re: Latches with weak memory ordering (Re: max_wal_senders must die)
Date: 2010-11-19 14:58:39
Message-ID: AANLkTikjwMonzTY_6qufx9bNuKDZXmJo6o2nXnqDAzZ4@mail.gmail.com
Views: Raw Message | Whole Thread | Download mbox | Resend email
Thread:
Lists: pgsql-hackers

On Fri, Nov 19, 2010 at 9:49 AM, Andres Freund <andres(at)anarazel(dot)de> wrote:
> Well, its not generally true - you are right there. But there is a wide range
> for syscalls available where its inherently true (which is what I sloppily
> referred to). And you are allowed to call a, although quite restricted, set of
> system calls even in signal handlers. I don't have the list for older posix
> versions in mind, but for 2003 you can choose something from several like
> write, lseek,setpgid which inherently have to serialize. And I am quite sure
> there were sensible calls for earlier versions.

Well, it's not quite enough just to call into the kernel to serialize
on "some point of memory", because your point is to make sure that
*this particular piece of memory* is coherent. It doesn't matter if
the kernel has proper fencing in it's stuff if the memory it's
guarding is in another cacheline, because that won't *necessarily*
force cache coherency in your local lock/variable memory.

--
Aidan Van Dyk                                             Create like a god,
aidan(at)highrise(dot)ca                                       command like a king,
http://www.highrise.ca/                                   work like a slave.

In response to

Responses

Browse pgsql-hackers by date

  From Date Subject
Next Message Tom Lane 2010-11-19 15:01:45 Re: Latches with weak memory ordering (Re: max_wal_senders must die)
Previous Message Shigeru HANADA 2010-11-19 14:55:15 Re: SQL/MED estimated time of arrival?