Re: Re: Misaligned BufferDescriptors causing major performance problems on AMD

On 2014-02-05 09:57:11 -0500, Tom Lane wrote:
> Andres Freund <andres(at)2ndquadrant(dot)com> writes:
> > On 2014-02-04 16:24:02 -0800, Peter Geoghegan wrote:
> >> I suspect that the scenario described in this article accounts for the
> >> quite noticeable effect reported: http://danluu.com/3c-conflict
>
> > I don't think that's applicable here.
>
> Maybe, or maybe not, but I think it does say that we should be very wary
> of proposals to force data structure alignment without any testing of the
> consequences.

I agree it needs testing, but what the page is talking about really,
really doesn't have *anything* to do with this. What the author is
talking about is not storing things *page* aligned (I.e. 4k or a
multiple). The problem is that the beginning of each such page falls
into the same cacheline set and thus doesn't utilize the entire L1/L2/L3
but only the single set they map into.

Greetings,

Andres Freund

--
Andres Freund http://www.2ndQuadrant.com/
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